Transposition circuit

ABSTRACT

The transposition circuit includes N input terminals (where N is an integer of 2 or greater) and N output terminals. This transposition circuit is configured such that when N packets of data for each matrix row are inputted in parallel to the corresponding input terminals, N packets of data are output in parallel for each matrix column from the corresponding output terminals. This transposition circuit generates data packets arranged as a transposed matrix and obtained from data packets in the form of an N×N matrix by interchanging the rows and columns of the original matrix.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a divisional application of application Ser. No. 09/584,549,filed Jun. 1, 2000, now abandoned, which is hereby incorporated byreference in its entirety for all purposes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to transposition circuit for transposingmatrix data (data packets in the form of matrices) in order, forexample, to perform discrete cosine transform or another procedure.

2. Description of Related Art

FIGS. 5(A)–5(C) are diagrams illustrating conventional transposition ofmatrix data. FIG. 5A is a block diagram depicting the structure of atransposition circuit. FIG. 5B is an image diagram depicting memorycontent. FIG. 5C is a timing chart depicting the operation of atransposition circuit.

A transposition circuit comprises a random-access memory (hereinafter“RAM”) 10 and an address generator 12, as shown in FIG. 5A. RAM 10 isequipped with an input port and an output port. The address generator 12generates a write address WA and a read address RA on the basis of aclock signal CK. Input data DI inputted to the input port of RAM 10 iswritten to the storage area in RAM 10 specified by the write address WA.To read data from RAM 10, the storage area in the RAM 10 where this datais stored is specified by the read address RA. The data thus read isoutputted as output data DO from the output port of RAM 10. The addressgenerator 12 can specify the write address WA and the read address RAseparately. Consequently, RAM 10 allows data to be read and writtenindependently and concurrently.

Such circuit architecture allows the read sequence of output data DO tobe varied in conformity with the write sequence of the input data DIsequentially inputted in matrix format. Output data DO can therefore beconverted to a transposed matrix format.

FIG. 5B depicts the storage areas of RAM 10. Numbers in the drawingindicate addresses of storage areas. In this example, data arranged as a4×4 matrix is processed, so 16 storage areas designated by symbols 0 to15 are provided to RAM 10.

Transposition of data arranged as a 4×4 matrix will now be describedwith reference to FIG. 5C.

During periods 0 to 15, the first 16 data d0 to d15 are inputted asinput data DI to RAM 10 according the aforementioned sequence in syncwith clock signals CK. The address generator 12 outputs write addressesWA 0 to 15 for the corresponding data d0 to d15. Data d0 to d15 arethereby stored to the corresponding addresses 0 to 15 of RAM 10.

During period 16, the address generator 12 generates address 0 as a readaddress RA. In accordance with this, data d0 stored at address 0 of RAM10 is outputted as output data DO. During period 16, the addressgenerator 12 also outputs address 0 as a write address WA. In accordancewith this, data d16 provided as input data DI is stored to address 0 ofRAM 10.

During period 17, the address generator 12 outputs address 4 as a readaddress RA. In accordance with this, data d4 stored at address 4 of RAM10 is outputted as output data DO. During period 17, the addressgenerator 12 also outputs address 4 as a write address WA. In accordancewith this, data d17 provided as input data DI is stored to address 4 ofRAM 10.

Similarly, during periods 18, 19, 20, 21, . . . the address generator 12outputs addresses 8, 12, 1, 5, . . . as read addresses RA. In accordancewith this, data d8, d12, d1, d5, . . . stored at addresses 8, 12, 1, 5,. . . of RAM 10 are outputted as output data DO. In these periods 18,19, 20, 21, . . . the address generator 12 also outputs addresses 8, 12,1, 5, . . . as write addresses WA. In accordance with this, data d18,d19, d20, d21, . . . provided as input data DI are stored to addresses8, 12, 1, 5, . . . of RAM 10.

Thus, data d0, d1, d2, and d3 corresponding to the components in thefirst row of the matrix are first written to RAM 10 in the orderindicated. Data d4, d5, d6, and d7 corresponding to the components inthe second row of the matrix are then written to RAM 10 in the orderindicated. Data d8, d9, d10, and d11 corresponding to the components inthe third row of the matrix are subsequently written to RAM 10 in theorder indicated. Data d12, d13, d14, and d15 corresponding to thecomponents in the fourth row of the matrix are written after that to RAM10 in the order indicated.

Data d0, d4, d8, and d12 corresponding to the components in the firstcolumn of the matrix are read from RAM 10 in the order indicated. Datad1, d5, d9, and d13 corresponding to the components in the second columnof the matrix are subsequently read from RAM 10 in the order indicated.Data d2, d6, d10, and d14 corresponding to the components in the thirdcolumn of the matrix are then read from RAM 10 in the order indicated.Data d3, d7, d11, and d15 corresponding to the components in the fourthcolumn of the matrix are read after that from RAM 10 in the orderindicated.

Matrix data inputted to the transposition circuit is thus converted todata arranged as a matrix obtained by interchanging the rows and columnsof the original matrix.

Conventional transposition circuits, however, are configured such that asingle data packet is read or written per period. A processing time of2N² periods will therefore be needed to process data arranged as an N×Nmatrix (where N is an integer of 2 or greater). A resulting disadvantageis that the processing time increases dramatically with increased matrixsize.

SUMMARY OF THE INVENTION

With the foregoing in view, it is an object of the present invention toprovide a transposition circuit having a shorter processing time than inthe past.

To attain the stated object, the transposition circuit of the presentinvention is provided with the following unique structure. Specifically,the transposition circuit of the present invention generates datapackets arranged as a transposed matrix and obtained from data packetsin the form of an N×N matrix (where N is an integer of 2 or greater) byinterchanging the rows and columns of the original matrix. According tothe present invention, the transposition circuit is provided with Ninput terminals and N output terminals. Another feature of the presentinvention is that N packets of data are outputted in parallel for eachmatrix column from the output terminals when N packets of data areinputted in parallel for each matrix row to the input terminals.

The rows and columns of matrices are thus interchanged because data isinputted by matrix row and outputted by matrix column. Data packetsarranged as a matrix can thereby be converted by this transpositioncircuit to data packets arranged as a transposed matrix in relation tothe original matrix.

Yet another feature of this transposition circuit is that processingspeed can be increased because a plurality of data packets can beprocessed in parallel during a single period. Specifically, theprocessing time is 2N periods because N data packets are processedduring each period. In other words, the processing time is reduced to1/N of conventional time.

According to a preferred embodiment of the present invention, thetransposition circuit is provided with a control unit and N×N registersarranged in N rows and N columns. A first column of registers and anN-th row of registers are coupled with input terminals, and a first rowof registers and an N-th column of registers are coupled with outputterminals. The control unit specifies a first transfer mode or a secondtransfer mode.

In the first transfer mode, data inputted to the input terminals isstored in the first column of registers, data stored in an n-th column(where n is an integer from 1 to (N−1)) of registers is transferred toan (n+1)-th column of registers, and data stored in an N-th column ofregisters is outputted to the output terminals.

In the second transfer mode, data inputted to the input terminals isstored in the N-th row of registers, data stored in an m-th row (where mis an integer from 2 to N) of registers is transferred to an (m−1)-throw of registers, and data stored in the first row of registers isoutputted to the output terminals.

In this transposition circuit, the control unit thus selects either thefirst column of registers or the N-th row of registers as the storagelocation for inputted data. In addition, the transposition circuit issuch that a plurality of registers are disposed between the inputterminals and output terminals, and the direction of data transferbetween the registers is controlled by the control unit. Another featureof this transposition circuit is that the control unit outputs datastored in a selected register by selecting either the N-th column ofregisters or the first row of registers. This structure allows datainputted by matrix row to be outputted by matrix column.

According to another preferred embodiment of the present invention, thetransposition circuit is provided with N×N registers arranged in N rowsand N columns, N×N first selectors whose output ports are individuallyconnected to the input ports of these registers, (N−1) second selectorswhose output ports are individually connected to the output terminals,and a control unit.

These first and second selectors have first and second ports. Either thefirst or second ports are used as input ports in accordance with controlsignals from the control unit.

The first ports of the first selectors in an i-th row and a first column(where i is an integer between 1 and N), and the second ports of thefirst selectors in an N-th row and (N+1−i)-th column are connected toNo. i input terminals. The output ports of the registers in an m-th rowand n-th column (where m is an integer between 2 and N, and n is aninteger between 1 and (N−1)) are connected to the second ports of thefirst selectors in an (m−1)-th row and n-th column and to the firstports of the first selectors in the m-th row and (n+1)-th column. Theoutput ports of the registers in the m-th row and N-th column areconnected to the first ports of No. (m−1) second selectors. The outputports of the registers in a first row and the n-th column are connectedto the second ports of No. (N−n) second selectors. The output ports ofthe registers in the first row and N-th column are connected to No. 1output terminals. The output ports of No. n second selectors areconnected to No. (n+1) output terminals.

In this transposition circuit, the control unit thus selects either thefirst column of registers or the N-th row of registers as the storagelocation for inputted data by selecting the input ports of the firstselectors. In addition, the transposition circuit is such that aplurality of registers are disposed between the input terminals andoutput terminals, and the direction of data transfer between theregisters is controlled by the control unit via the first selectors.Another feature of this transposition circuit is that the control unitselects either the N-th column of registers or the first row ofregisters and outputs data stored in selected registers by selecting theinput ports of the second selectors. This structure allows data inputtedby matrix row to be outputted by matrix column.

According to yet another preferred example of the present invention, thetransposition circuit is provided with N memory units whose storageareas accommodate N data packets, N first selectors whose output portsare individually connected to the input ports of these memory units, Nsecond selectors whose output ports are individually connected to theoutput terminals, and a control unit.

The first and second selectors have N ports. Any of these ports is usedas an input port for the first and second selectors in accordance withselection signals from the control unit.

The ports of the first selectors are connected to the correspondinginput terminals. The ports of the second selectors are connected to theoutput ports of the corresponding memory units.

The control unit specifies prescribed storage areas in the memory unitsand generates, together with the selection signals, address signals forreading data from the memory units and writing data to the memory units.

With the transposition circuit thus configured, data inputted inparallel by row to the input terminals is sent to the prescribed portsof first selectors. The prescribed ports of the first selectors areselected as input ports by the selection signals from the control unit,and data sent to these input ports is stored in the prescribed memoryunits. Data inputted in parallel is therefore stored in separate memoryunits. The data storage locations in the memory units are specified bythe address signals from the control unit.

Data stored at the storage locations specified by the address signals isread from the memory in accordance with address signals from the controlunit. The data thus read is sent to the prescribed ports of secondselectors. The prescribed ports of the second selectors are selected asinput ports by the selection signals from the control unit. Data sent tothese input ports is outputted to prescribed output terminals. Thisstructure allows data inputted by matrix row to be outputted by matrixcolumn.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages of the presentinvention will be better understood from the following description takenin connection with the accompanying drawings, in which:

FIG. 1 is a block diagram depicting the transposition circuit of a firstembodiment;

FIG. 2 is a timing chart depicting the operation of the transpositioncircuit of the first embodiment;

FIG. 3 is a block diagram depicting the transposition circuit of asecond embodiment;

FIG. 4 is a timing chart depicting the operation of the transpositioncircuit of the second embodiment; and

FIGS. 5A, 5B, and 5C are diagrams illustrating conventionaltransposition of matrix data.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the transposition circuit of the present invention willnow be described through examples with reference to drawings. Thedrawings used in the description are merely schematic representations ofthe manner in which constituent components are arranged or connected inrelation to each other. These drawings are used solely to illustrate thepresent invention. The same symbols are used in the drawings todesignate identical constituent components, and redundant descriptionsthereof are sometimes omitted. In addition, the devices, numericalconditions, and other elements referred to hereinbelow are merelyexamples that do not exceed the scope of the present invention, which isnot limited by these examples.

EXAMPLE 1

FIG. 1 is a block diagram depicting the structure of the transpositioncircuit of the first embodiment. This transposition circuit generatesdata packets arranged as a transposed matrix and obtained from datapackets in the form of an N×N matrix (where N is a integer of 2 orgreater; in the case under consideration, N=4) by interchanging the rowsand columns of the original matrix.

The transposition circuit comprises N input terminals 14 _(i) (where iis an integer between 1 and N) and N output terminals 16 _(i). Thistransposition circuit is configured such that when N packets of data areinputted in parallel for each matrix row to the corresponding inputterminals 14 _(i), N packets of data are outputted in parallel for eachmatrix column from the corresponding output terminals 16 _(i).

The transposition circuit also comprises a control unit 20 and N×Nregisters 18 _(i,j) (where i and j are integers between 1 and N)arranged in N rows and N columns. The transposition circuit furthercomprises N×N first selectors 22 _(i,j) whose output ports areindividually connected to the input ports of the registers 18 _(i,j).The transposition circuit additionally comprises (N−1) second selectors24 _(n) whose output ports are individually connected to outputterminals 16 _(n+1) (where n is an integer between 1 and (N−1)).

The aforementioned first selectors 22 _(i,j) and second selectors 24_(n) have first and second ports, respectively. The first or secondports are used as input ports for the first selectors 22 _(i,j) andsecond selectors 24 _(n), in accordance with control signals S from thecontrol unit 20.

The aforementioned control unit 20 generates control signals S for thefirst selectors 22 _(i,j) and second selectors 24 _(n) on the basis ofclock signals CK. For example, the first selectors 22 _(i,j) and thesecond selectors 24 _(n) select first ports as the input ports (firsttransfer mode) when the control signals S are logical zeros, and secondports as the input ports (second transfer mode) when the control signalsS are logical ones. The transposition circuit thus operates in atransfer mode that corresponds to the logical values of the controlsignals S.

In the transposition circuit, the first port of a first selector 22_(i,1) in an i-th row and a first column and the second port of a firstselector 22 _(i, N+1−i) in an N-th row and (N+1−i)-th column areconnected to No. i input terminal 14 _(i).

The output port of a register 18 _(m,n) in an m-th row and n-th column(where m is an integer between 2 and N, and n is an integer between 1and (N−1)) is connected to the second port of a first selector 22_(m−1,n) in an (m−1)-the row and n-th column and to the first port of afirst selector 22 _(m, n+1) in an m-th row and (n+1)-th column.

The output port of register 18 _(m,N) in an m-th row and N-th column isconnected to the first port of No. (m−1) second selector 24 _(m−1).

The output port of register 18 _(1,n) in a first row and an n-th columnis connected to the second port of No. (N−n) second selector 24 _(N−n).

The output port of register 18 _(1,N) in the first row and N-th columnis connected to No. 1 output terminal 16 _(i).

The output port of No. n second selector 24 _(n) is connected to No.(n+1) output terminal 16 _(n+1).

The registers 18 _(i,1) of the first column are thus coupled with theinput terminals 14 _(i) via the first selectors 22 _(i,1). The registers18 _(N,j) of the N-th row are coupled with the input terminals 14 _(i)via the first selectors 22 _(N,j). The registers 18 _(1,j) of the firstrow are coupled with the output terminals 16 _(i) either directly or viathe second selectors 24 _(n). The registers 18 _(i,N) of the N-th columnare coupled with the output terminals 16 _(i) either directly or via thesecond selectors 24 _(n).

With this transposition circuit, data inputted to an input terminal 14_(i) is stored in a register 18 _(i,1) in the first column when thecontrol unit 20 specifies the first transfer mode. At the same time,data stored in register 18 _(i,n) in the n-th column is transferred toregister 18 _(i, n+1) in the (n+1)-th column, and data stored inregister 18 _(N,j) in the N-th column is outputted to the outputterminal 16 _(i).

Data inputted to an input terminal 14 _(i) is stored in a register 18_(N,j) in the N-th row when the control unit 20 specifies the secondtransfer mode. At the same time, data stored in register 18 _(m,j) inthe m-th row is transferred to register 18 _(m−1, j) in the (m−1)-throw, and data stored in register 18 _(i,j) in the first row is outputtedto the output terminal 16 _(i).

The operation of the transposition circuit of the first embodiment willnow be described in detail with reference to FIG. 2. FIG. 2 is a timingchart depicting the operation of the transposition circuit of the firstembodiment.

In this transposition circuit, data d0 to d15, d16 to d31, d32 to d47, .. . in a 4×4 matrix format are inputted in parallel as input data DI_(i)in groups of four packets to input terminals 14 _(i). The data isoutputted in parallel as output data DO_(i) in groups of four packetsfrom output terminals 16 _(i).

The logical value of the control signal S outputted by the control unit20 during periods 0 to 3 is set to 0, as shown in FIG. 2. In accordancewith this, the transposition circuit operates in the above-describedfirst transfer mode during periods 1 to 4.

During period 0, data d0 to d3 are inputted to input terminals 14 ₁ to14 ₄ as input data DI₁ to D₄, respectively.

During period 1, the data d0, d1, d2, and d3 inputted to the inputterminals 14 ₁ to 14 ₄ during period 0 are written to the registers 18_(1,1), 18 _(2,1), 18 _(3,1), and 18 _(4,1), respectively, via the firstselectors 22 _(1,1), 22 _(2,1), 22 _(3,1), and 22 _(4,1). During period1, data d4 to d7 are also inputted as input data DI₁ to DI₄ to the inputterminals 14 ₁ to 14 ₄, respectively.

During period 2, the data d0, d1, d2, and d3 stored in the registers 18_(1,1) to 18 _(4,1) during period 1 are written to the registers 18_(1,2), 18 _(2,2), 18 _(3,2), and 18 _(4,2), respectively, via the firstselectors 22 _(1,2), 22 _(2,2), 22 _(3,2), and 22 _(4,2). During period2, the data d4, d5, d6, and d7 inputted to the input terminals 14 ₁ to14 ₄ during period 1 are written to the registers 18 _(1,1), 18 _(2,1),18 _(3,1), and 18 _(4,1), respectively, via the first selectors 22_(1,1), 22 _(2,1), 22 _(3,1), and 22 _(4,1). During period 2, data d8 tod11 are also inputted as input data DI₁ to DI₄ to the input terminals 14₁ to 14 ₄, respectively.

During period 3, the data d0, d1, d2, and d3 stored in the registers 18_(1,2) to 18 _(4,2) during period 2 are written to the registers 18_(1,3), 18 _(2,3), 18 _(3,3), and 18 _(4,3), respectively, via the firstselectors 22 _(1,3), 22 _(2,3), 22 _(3,3), and 22 _(4,3). During period3, the data d4, d5, d6, and d7 stored in the registers 18 ₁, to 18_(4,1) during period 2 are written to the registers 18 _(1,2), 18_(2,2), 18 _(3,2), and 18 _(4,2), respectively, via the first selectors22 _(1,2), 22 _(2,2), 22 _(3,2), and 22 _(4,2). During period 3, thedata d8, d9, d10, and d11 inputted to the input terminals 14 ₁ to 14 ₄during period 2 are written to the registers 18 _(1,1), 18 _(2,1), 18_(3,1), and 18 _(4,1), respectively, via the first selectors 22 _(1,1),22 _(2,1), 22 _(3,1), and 22 _(4,1). During period 3, data d12 to d15are also inputted as input data DI₁ to DI₄ to the input terminals 14 ₁to 14 ₄, respectively.

During period 4, the data d0, d1, d2, and d3 stored in the registers 18_(1,3) to 18 _(4,3) during period 3 are written to the registers 18_(1,4), 18 _(2,4), 18 _(3,4), and 18 _(4,4), respectively, via the firstselectors 22 _(1,4), 22 _(2,4), 22 _(3,4), and 22 _(4,4). During period4, the data d4, d5, d6, and d7 stored in the registers 18 _(1,2) to 18_(4,2) during period 3 are written to the registers 18 _(1,3), 18_(2,3), 18 _(3,3), and 18 _(4,3), respectively, via the first selectors22 _(1,3), 22 _(2,3), 22 _(3,3), and 22 _(4,3). During period 4, thedata d8, d9, d10, and d11 stored in the registers 18 _(1,1) to 18 _(4,1)during period 3 are written to the registers 18 _(1,2), 18 _(2,2), 18_(3,2), and 18 _(4,2), respectively, via the first selectors 22 _(1,2),22 _(2,2), 22 _(3,2), and 22 _(4,2). During period 4, the data d12, d13,d14, and d15 inputted to the input terminals 14 ₁ to 14 ₄ during period3 are written to the registers 18 _(1,1), 18 _(2,1), 18 _(3,1), and 18_(4,1), respectively, via the first selectors 22 _(1,1) 22 _(2,1), 22_(3,1), and 22 _(4,1). During period 4, data d16 to d19 are alsoinputted as input data DI₁ to DI₄ to the input terminals 14 ₁ to 14 ₄,respectively.

Data is thus transferred in the direction of the row arrangement of theregisters 18 _(i,j) during periods 1 to 4.

During period 4, the logical value of the control signal S outputted bythe control unit 20 is switched to “1.” During the subsequent periods 4to 7, the logical value of the control signal S outputted by the controlunit 20 is set to “1.” Consequently, the transposition circuit operatesin the above-described second transfer mode during periods 5 to 8.

During period 5, the data d0, d4, d8, and d12 stored in the registers 18_(1,4), 18 _(1,3), 18 _(1,2), and 18 _(1,1) during period 4 areoutputted to the output terminals 16 ₁, 16 ₂, 16 ₃, and 16 ₄,respectively, either directly or via the second selectors 24 ₁ to 24 ₃.

During period 5, the data d1, d5, d9, and d13 stored in the registers 18_(2,4), 18 _(2,3), 18 _(2,2), and 18 _(2,1) during period 4 are writtento the registers 18 _(1,4), 18 _(1,3), 18 _(1,2), and 18 _(1,1),respectively, via the first selectors 22 _(1,4), 22 _(1,3), 22 _(1,2),and 22 _(1,1). During period 5, the data d2, d6, d10, and d14 stored inthe registers 18 _(3,4), 18 _(3,3), 18 _(3,2), and 18 _(3,1) duringperiod 4 are also written to the registers 18 _(2,4), 18 _(2,3), 18_(2,2), and 18 _(2,1), respectively, via the first selectors 22 _(2,4),22 _(2,3), 22 _(2,2), and 22 _(2,1). During period 5, the data d3, d7,d11, and d15 stored in the registers 18 _(4,4), 18 _(4,3), 18 _(4,2),and 18 _(4,1) during period 4 are also written to the registers 18_(3,4), 18 _(3,3), 18 _(3,2), and 18 _(3,1), respectively, via the firstselectors 22 _(3,4), 22 _(3,3), 22 _(3,2), and 22 _(3,1). During period5, the data d16, d17, d18, and d19 inputted to the input terminals 14 ₁to 14 ₄ during period 4 are also written to the registers 18 _(4,4), 18_(4,3), 18 _(4,2), and 18 _(4,1), respectively, via the first selectors22 _(4,4), 22 _(4,3), 22 _(4,2), and 22 _(4,1). During period 5, datad20 to d23 are also inputted as input data DI₁ to DI₄ to the inputterminals 14 ₁ to 14 ₄, respectively.

Similarly, data is transferred in the direction of the columnarrangement of the registers 18 _(i,j) during periods 6 to 8.Consequently, data d1, d5, d9, and d13 are outputted from the outputterminals 16 ₁, 16 ₂, 16 ₃, and 16 ₄, respectively, during period 6.During period 7, data d2, d6, d10, and d14 are outputted from the outputterminals 16 ₁, 16 ₂, 16 ₃, and 16 ₄, respectively. During period 8,data d3, d7, d11, and d15 are outputted from the output terminals 16 ₁,16 ₂, 16 ₃, and 16 ₄, respectively.

During period 8, the logical value of the control signal S outputted bythe control unit 20 is switched to “0.” During the subsequent periods 8to 11, the logical value of the control signal S outputted by thecontrol unit 20 is set to “0.” Consequently, the transposition circuitoperates in the above-described first transfer mode during periods 9 to12. Data is thus transferred in the direction of the row arrangement ofthe registers 18 _(i,j) during periods 9 to 12.

Consequently, data d16, d20, d24, and d28 are outputted from the outputterminals 16 ₁ to 16 ₄, respectively, during period 9. During period 10,data d17, d21, d25, and d29 are outputted from the output terminals 16 ₁to 16 ₄, respectively. During period 11, data d18, d22, d26, and d30 areoutputted from the output terminals 16 ₁ to 16 ₄, respectively. Duringperiod 12, data d19, d23, d27, and d31 are outputted from the outputterminals 16 ₁ to 16 ₄, respectively.

The transposition circuit then continues to change the data arrangementsequence while switching between transfer modes every four periods.

The transposition circuit thus outputs data in parallel in packets offour for each matrix column when this data is inputted in parallel inpackets of four for each matrix row. In other words, data packetsinputted as a matrix are outputted as data packets in the form of atransposed matrix obtained by interchanging the rows and columns of theoriginal matrix.

In addition, the time needed to process the data packets of a singlematrix corresponds to 2N periods because N data packets are processed bythe transposition circuit during each period. The processing time isthus reduced to 1/N of conventional time.

Another feature of the proposed transposition circuit is that it issufficient for the control signal S of the control unit 20 to bealternated between “0” and “1” in matrix units. This transpositioncircuit is therefore advantageous in that it has a comparatively simplecircuit architecture.

The first selector 22 _(N,1) (corresponds to the first selectors 22_(4,1) in FIG. 1) in the first column and the N-th row may also bedispensed with. In the absence of the first selector 22 _(N,1), No. Ninput terminal 14 _(N) should be connected directly to the input port ofthe register 18 _(N,1) in the first column and the N-th row.

EXAMPLE 2

FIG. 3 is a block diagram depicting the structure of the transpositioncircuit of a second embodiment. This transposition circuit generatesdata packets arranged as a transposed matrix and obtained from datapackets in the form of an N×N matrix (where N is a integer of 2 orgreater; in the case under consideration, N=4) by interchanging the rowsand columns of the original matrix.

The transposition circuit comprises N input terminals 14 _(i) (where iis an integer between 1 and N) and N output terminals 16 _(i). Thistransposition circuit is configured such that when N packets of data areinputted in parallel for each matrix row to the corresponding inputterminals 14 _(i), N packets of data are outputted in parallel for eachmatrix column from the corresponding output terminals 16 _(i).

The transposition circuit is also provided with N units of random accessmemory (hereinafter “RAM”) 26 _(i) whose storage areas are used to storeN packets of data. RAM 26 _(i) has input ports and output ports. Thetransposition circuit also has N first selectors 28 _(i) whose outputports are individually connected to the input ports of the memory 26_(i). The transposition circuit further has N second selectors 30 _(i)whose output ports are individually connected to output terminals 16_(i). The transposition circuit also has a control unit 32.

The aforementioned first selectors 28 _(i) and second selectors 30 _(i)have N input ports for each type of selector. Ports of either type areused as input ports for the first selectors 28 _(i) and second selectors30 _(i) in accordance with selection signals SL from the control unit32.

The aforementioned control unit 32 generates selection signals SL forthe first selectors 28 _(i) and second selectors 30 _(i) on the basis ofclock signals CK. For example, the first selectors 28 _(i) and thesecond selectors 30 _(i) select first, second, third, and fourth portsas input ports when the selection signals SL assume the values of 0, 1,2, and 3.

The above-described control unit 32 generates selection signals SL andproduces address signals A_(i) for RAM 26 _(i) on the basis of clocksignals CK. Prescribed storage areas of RAM 26 _(i) are specified inaccordance with the values of the address signals A_(i), and data isread from and written to the specified storage areas. For example,addresses 0, 1, 2, and 3 are specified as the storage areas of RAM 26_(i) when the address signals A_(i) assume the values of 0, 1, 2, and 3.In the transposition circuit, read addresses and write addresses arespecified by common address signals A_(i) because data is read from andwritten to common storage areas during any given period.

In the transposition circuit, the ports of the first selectors 28 _(i)are connected to the corresponding input terminals 14 _(j) (where j isan integer between 1 and N) Specifically, No. 1 input terminal 14 ₁ isconnected to the first port of No. 1 first selector 28 ₁, the secondport of No. 2 first selector 28 ₂, the third port of No. 3 firstselector 28 ₃, and the fourth port of No. 4 first selector 28 ₄.

No. 2 input terminal 14 ₂ is connected to the fourth port of No. 1 firstselector 28 ₁, the first port of No. 2 first selector 28 ₂, the secondport of No. 3 first selector 28 ₃, and the third port of No. 4 firstselector 28 ₄.

No. 3 input terminal 14 ₃ is connected to the third port of No. 1 firstselector 28 ₁, the fourth port of No. 2 first selector 28 ₂, the firstport of No. 3 first selector 28 ₃, and the second port of No. 4 firstselector 28 ₄.

No. 4 input terminal 14 ₄ is connected to the second port of No. 1 firstselector 28 ₁, the third port of No. 2 first selector 28 ₂, the fourthport of No. 3 first selector 28 ₃, and the first port of No. 4 firstselector 28 ₄.

In the transposition circuit, the input ports of the second selectors 30_(i) are connected to the output terminals of the corresponding RAM 26_(i).

Specifically, the output port of No. 1 RAM 26 ₁ is connected to thefirst port of No. 1 second selector 30 ₁, the fourth port of No. 2second selector 30 ₂, the third port of No. 3 second selector 30 ₃, andthe second port of No. 4 second selector 30 ₄.

The output port of No. 2 RAM 26 ₂ is connected to the second port of No.1 second selector 30 ₁, the first port of No. 2 second selector 30 ₂,the fourth port of No. 3 second selector 30 ₃, and the third port of No.4 second selector 30 ₄.

The output port of No. 3 RAM 26 ₃ is connected to the third port of No.1 second selector 30 ₁, the second port of No. 2 second selector 30 ₂,the first port of No. 3 second selector 30 ₃, and the fourth port of No.4 second selector 30 ₄.

The output port of No. 4 RAM 26 ₄ is connected to the fourth port of No.1 second selector 30 ₁, the third port of No. 2 second selector 30 ₂,the second port of No. 3 second selector 30 ₃, and the first port of No.4 second selector 30 ₄.

In this transposition circuit, data inputted in parallel to the inputterminals 14 _(i) for each row is sent to the prescribed ports of thefirst selectors 28 _(j). Prescribed ports of the first selectors 28 _(j)are selected as input ports in accordance with selection signals fromthe control unit 32. Data sent to these input ports is stored inprescribed RAM 26 _(j). Consequently, data packets inputted in parallelare stored in individual RAM 26 _(j). The storage location of data ineach RAM 26 _(j) is specified by address signals A_(j) from the controlunit 32.

Data stored in the storage areas specified by the address signals A_(j)is read from RAM 26 _(j) in accordance with the address signals A_(j)from the control unit 32. The data thus read is sent to the prescribedports of second selectors 30 _(i). Prescribed ports of the secondselectors 30 _(i) are selected as input ports in accordance withselection signals from the control unit 32. Data sent to these inputports is outputted to prescribed output terminals 16 _(i).

The operation of the transposition circuit of the second embodiment willnow be described in detail with reference to FIG. 4. FIG. 4 is a timingchart depicting the operation of the transposition circuit of the secondembodiment.

In this transposition circuit, data d0 to d15, d16 to d31, d32 to d47, .. . in a 4×4 matrix format are inputted in parallel as input data DI_(i)in groups of four packets to input terminals 14 _(i). The data isoutputted in parallel as output data DO_(i) in groups of four packetsfrom output terminals 16 _(i).

In this transposition circuit, eight periods are needed to process adata packet corresponding to a single matrix. Of the eight periods, thefirst four periods are used to count up the values of selection signalsSL and address signals A_(i) from 0 to 3 in increments of one for eachperiod. The last four periods are used to count up the values of theselection signals SL from 0 to 3 in increments of one for each period.The values of the address signals A_(i) are counted down according toquaternary notation in increments of one for each period, with (i−1) asthe initial value. During the last four periods, therefore, the value ofthe address signal A₁ changes in the order 0, 3, 2, 1 with each period,with 0 as the initial value. Similarly, the value of the address signalA₂ changes in the order 1, 0, 3, 2 with each period, with 1 as theinitial value. Similarly, the value of the address signal A₃ changes inthe order 2, 1, 0, 3 with each period, with 2 as the initial value.Similarly, the value of the address signal A₄ changes in the order 3, 2,1, 0 with each period, with 3 as the initial value.

During period 0, which is shown in FIG. 4, the values of the selectionsignals SL and address signals A_(i) outputted from the control unit 32are all set to 0. At this time, data d0 to d3 are inputted as input dataDI₁ to DI₄ to the input terminals 14, to 14 ₄, respectively. Thedestination for the data d0 to d3 transferred during the subsequentperiod 1 is determined based on the corresponding values of theselection signals SL and address signals A_(i).

Specifically, during period 1 first ports are used as input ports forthe first selectors 28, to 28 ₄. During period 1, therefore, the datado, d1, d2, and d3 inputted to the input terminals 14 ₁ to 14 ₄ duringperiod 0 are written to the corresponding RAM 26 ₁, 26 ₂, 26 ₃, and 26 ₄via the first selectors 28 ₁, 28 ₂, 28 ₃, and 28 ₄. In addition, thedata d0, d1, d2, and d3 are written to addresses 0 of the correspondingRAM 26 ₁, 26 ₂, 26 ₃, and 26 ₄.

During period 1, the values of the selection signals SL and addresssignals A_(i) outputted from the control unit 32 are all set to 1. Atthis time, data d4 to d7 are inputted as input data DI₁ to DI₄ to theinput terminals 14 ₁ to 14 ₄, respectively. The destination for the datad4 to d7 transferred during the subsequent period 2 is determined basedon the corresponding values of the selection signals SL and addresssignals A_(i).

Specifically, during period 2 second ports are used as input ports forthe first selectors 28 ₁ to 28 ₄. During period 2, therefore, the datad4, d5, d6, and d7 inputted to the input terminals 14 ₁ to 14 ₄ duringperiod 1 are written to the corresponding RAM 26 ₂, 26 ₃, 26 ₄, and 26 ₁via the first selectors 28 ₂, 28 ₃, 28 ₄, and 28 ₁. In addition, thedata d4, d5, d6, and d7 are written to addresses 1 of the correspondingRAM 26 ₂, 26 ₃, 26 ₄, and 26 ₁.

During period 2, the values of the selection signals SL and addresssignals A_(i) outputted from the control unit 32 are all set to 2. Atthis time, data d8 to d11 are inputted as input data DI₁ to DI₄ to theinput terminals 14 ₁ to 14 ₄, respectively. The destination for the datad8 to d11 transferred during the subsequent period 3 is determined basedon the corresponding values of the selection signals SL and addresssignals A_(i).

Specifically, during period 3 third ports are used as input ports forthe first selectors 28 ₁ to 28 ₄. During period 3, therefore, the datad8, d9, d10, and d11 inputted to the input terminals 14 ₁ to 14 ₄ duringperiod 2 are written to the corresponding RAM 26 ₃, 26 ₄, 26 ₁, and 26 ₂via the first selectors 28 ₃, 28 ₄, 28 ₁, and 28 ₂. In addition, thedata d8, d9, d10, and d11 are written to addresses 2 of thecorresponding RAM 26 ₃, 26 ₄, 26 ₁, and 26 ₂.

During period 3, the values of the selection signals SL and addresssignals A_(i) outputted from the control unit 32 are all set to 3. Atthis time, data d12 to d15 are inputted as input data DI₁ to DI₄ to theinput terminals 14 ₁ to 14 ₄, respectively. The destination for the datad12 to d15 transferred during the subsequent period 4 is determinedbased on the corresponding values of the selection signals SL andaddress signals A_(i).

Specifically, during period 4 fourth ports are used as input ports forthe first selectors 28 ₁ to 28 ₄. During period 4, therefore, the datad12, d13, d14, and d15 inputted to the input terminals 14 ₁ to 14 ₄during period 3 are written to the corresponding RAM 26 ₄, 26 ₁, 26 ₂,and 26 ₃ via the first selectors 28 ₄, 28 ₁, 28 ₂, and 28 ₃. Inaddition, the data d12, d13, d14, and d15 are written to addresses 3 ofthe corresponding RAM 26 ₄, 26 ₁, 26 ₂, and 26 ₃.

During period 4, the control unit 32 sets the value of the selectionsignal SL to 0, the value of the address signal A₁ to 0, the value ofthe address signal A₂ to 1, the value of the address signal A₃ to 2, thevalue of the address signal A₄ to 3. At this time, data d16 to d19 areinputted as input data DI₁ to DI₄ to the input terminals 14 ₁ to 14 ₄,respectively. The destination for the data d16 to d19 transferred duringthe subsequent period 5 is determined based on the corresponding valuesof the selection signals SL and address signals A_(i).

During period 5, data stored in prescribed storage areas of RAM 26 _(i)is first read based on the address signals A_(i) set during period 4.Specifically, the following data packets are read: data d0 stored ataddress 0 of RAM 26 ₁, data d4 stored at address 1 of RAM 26 ₂, data d8stored at address 2 of RAM 26 ₃, and data d12 stored at address 3 of RAM26 ₄. During period 5, first ports are used as input ports for thesecond selectors 30 ₁ to 30 ₄ on the basis of the values of theselection signals SL set during period 4. Consequently, data d0, d4, d8,and d12 that have been read from RAM 26 _(i) are outputted as outputdata DO₁ to DO₄ from the corresponding output terminals 16 ₁, 16 ₂, 16₃, and 16 ₄ via the second selectors 30 ₁, 30 ₂, 30 ₃, and 30 ₄.

During period 5, first ports are used as input ports for the firstselectors 28 ₁ to 28 ₄. During period 5, therefore, the data d16, d17,d18, and d19 inputted to the input terminals 14 ₁ to 14 ₄ during period4 are written to the corresponding RAM 26 ₁, 26 ₂, 26 ₃, and 26 ₄ viathe first selectors 28 ₁, 28 ₂, 28 ₃, and 28 ₄. These data d16, d17,d18, and d19 are written to address 0 of RAM 26 ₁, address 1 of RAM 26₂, address 2 of RAM 26 ₃, and address 3 of RAM 26 ₄, respectively.

During period 5, the control unit 32 sets the value of the selectionsignal SL to 1, the value of the address signal A₁ to 3, the value ofthe address signal A₂ to 0, the value of the address signal A₃ to 1, thevalue of the address signal A₄ to 2. At this time, data d20 to d23 areinputted as input data DI₁ to DI₄ to the input terminals 14 ₁ to 14 ₄,respectively. The destination for the data d20 to d23 transferred duringthe subsequent period 6 is determined based on the corresponding valuesof the selection signals SL and address signals A_(i).

During period 6, data stored in prescribed storage areas of RAM 26 _(i)is first read based on the address signals A_(i) set during period 5.Specifically, the following data packets are read: data d13 stored ataddress 3 of RAM 26 ₁, data d1 stored at address 0 of RAM 26 ₂, data d5stored at address 1 of RAM 26 ₃, and data d9 stored at address 2 of RAM26 ₄. During period 6, second ports are used as input ports for thesecond selectors 30 ₁ to 30 ₄ on the basis of the values of theselection signals SL set during period 5. Consequently, data d1, d5, d9,and d13 that have been read from RAM 26 _(i) are outputted as outputdata DO₁ to DO₄ from the corresponding output terminals 16 ₁, 16 ₂, 16₃, and 16 ₄ via the second selectors 30 ₁, 30 ₂, 30 ₃, and 30 ₄.

During period 6, second ports are used as input ports for the firstselectors 28 ₁ to 28 ₄. During period 6, therefore, the data d20, d21,d22, and d23 inputted to the input terminals 14 ₁ to 14 ₄ during period5 are written to the corresponding RAM 26 ₂, 26 ₃, 26 ₄, and 26 ₁ viathe first selectors 28 ₂, 28 ₃, 28 ₄, and 28 ₁. These data d20, d21,d22, and d23 are written to address 0 of RAM 26 ₂, address 1 of RAM 26₃, address 2 of RAM 26 ₄, and address 3 of RAM 26 ₁, respectively.

The values of the selection signals SL and address signals A_(i) foreach period are thus set in accordance with the above-describedprescribed sequence to control the storage locations of data written toRAM 26 _(i) and the sequence for reading data from RAM 26 _(i). Datapackets arranged as a matrix can be transposed as a result.

The transposition circuit thus outputs data in parallel in packets offour for each matrix column when this data is inputted in parallel inpackets of four for each matrix row. In other words, data packetsinputted as a matrix are outputted as data packets in the form of atransposed matrix obtained by interchanging the rows and columns of theoriginal matrix.

In addition, the time needed to process the data packets of a singlematrix corresponds to 2N periods because N data packets are processed bythe transposition circuit during each period. The processing time isthus reduced to 1/N of conventional time.

Another advantage of the proposed transposition circuit is that datapackets arranged as a matrix of any size (N or less) can be processedwithout modifying the circuitry as a result of the fact that theselection signals SL and address signals A_(i) generated by the controlunit 32 can be made programmable.

The present invention is not limited by the above-described examples andcan be modified in a variety of ways. Examples of such modifications aredescribed as (a) to (c) below.

(a) The invention is not limited by a 4×4 matrix and can be adapted toany N×N square matrix.

(b) The RAM 26 _(i) in FIG. 3 are 2-port RAM devices, but because thereading addresses and writing addresses are the same, it is possible touse regular RAM devices by setting write timing on the basis of writecontrol signals.

(c) Although the transposition circuits in the above examples weredescribed with reference to cases in which data was sequentiallyinputted by matrix row and was sequentially read by matrix column, it isalso possible to use an arrangement in which data is sequentiallyinputted by matrix column and is sequentially read by matrix row.

1. A transposition circuit for generating data packets arranged as atransposed matrix and obtained from data packets in the form of an N×Nmatrix (where N is an integer of 2 or greater) by interchanging rows andcolumns of an original matrix, wherein N input terminals and N outputterminals are provided; wherein N packets of data are output in parallelfor each matrix column from said output terminals when N packets of dataare input in parallel for each matrix row to said input terminals;wherein the transposition circuit is provided with N memory units havingstorage areas to accommodate N data packets, N input selectors havingoutput ports individually connected to input ports of the memory units,N output selectors having output ports individually connected to saidoutput terminals, and a control unit; wherein said input and outputselectors having N ports, and any of the ports of said input and outputselectors are used as an input port in accordance with a commonselection signal from said control unit to said input and outputselectors; wherein the ports of said input selectors are connected tocorresponding ones of the input terminals; wherein the ports of saidoutput selectors are connected to output ports of corresponding ones ofthe memory units; and wherein said control unit generates the commonselection signal, and produces address signals to specify a commonstorage area for each of the memory units, to both read data from andwrite data to the common storage areas during a same period.
 2. Thetransposition circuit of claim 1, wherein the memory units are units ofrandom access memory.
 3. The transposition circuit of claim 1, wherein Nis
 4. 4. The transposition circuit of claim 3, wherein the first inputterminal is connected to the first port of the first input selector, thesecond port of the second input selector, the third port of the thirdinput selector, and the fourth port of the fourth input selector;wherein the second input terminal is connected to the fourth port of thefirst input selector, the first port of the second input selector, thesecond port of the third input selector, and the third port of thefourth input selector; wherein the third input terminal is connected tothe third port of the first input selector, the fourth port of thesecond input selector, the first port of the third input selector, andthe second port of the fourth input selector; wherein the fourth inputterminal is connected to the second port of the first input selector,the third port of the second input selector, the fourth port of thethird input selector, and the first port of the fourth input selector;wherein the first through fourth input selectors have output portsindividually connected to the input ports of the first through fourthmemory units; wherein the output port of the first memory unit isconnected to the first port of the first output selector, the fourthport of the second output selector, the third port of the third outputselector, and the second port of the fourth output selector; wherein theoutput port of the second memory unit is connected to the second port ofthe first output selector, the first port of the second output selector,the fourth port of the third output selector, and the third port of thefourth output selector; wherein the output port of the third memory unitis connected to the third port of the first output selector, the secondport of the second output selector, the first port of the third outputselector, and the fourth port of the fourth output selector; wherein theoutput port of the fourth memory unit is connected to the fourth port ofthe first output selector, the third port of the second output selector,the second port of the third output selector, and the first port of thefourth output selector; and wherein the output ports of the firstthrough fourth output selectors are individually connected to the firstthrough fourth output terminals.
 5. The transposition circuit of claim4, wherein the memory units are units of random access memory.
 6. Thetransposition circuit of claim 4, wherein a data packet corresponding toa single 4×4 matrix is processed in eight periods; wherein during afirst four periods, values of said selection signal and i addresssignals increase from 0 to 3 in increments of one for each period;wherein during a last four periods, the values of said selection signalincreases from 0 to 3 in increments of one for each period and the iaddress signals decrease in increments of one for each period with (i−1)as an initial value; wherein the first through fourth input selectorsand the first through fourth output selectors select the first, second,third, and fourth ports of the memory units as input ports when theselection signals respectively assume values of 0, 1, 2 and 3; andwherein when the address signals assume values of 0, 1, 2 and 3, the iaddress signals specify addresses 0, 1, 2, and 3 as common storage areasof the memory units, respectively.
 7. The transposition circuit of claim1, wherein the memory units are units of 2-port random access memory. 8.A transposition circuit comprising: N input terminals, wherein N is aninteger greater than 2; N output terminals; N input selectors eachhaving N input ports coupled to the N input terminals and each having anoutput port, the N input selectors providing data from one of the inputports as an output responsive to a common selection signal; N memoryunits having storage areas for N packets of data and each having aninput port coupled to respectively different ones of the output ports ofthe N input selectors; N output selectors each having N input portscoupled to the output ports of the N memory units and each having anoutput port coupled to respectively different ones of the N outputterminals, the N output selectors respectively providing data from oneof the input ports thereof as an output responsive to the commonselection signal; and a controller that provides the common selectionsignal, and that provides address signals to the N memory units todesignate common storage areas, wherein data is both written into andread out from the common storage areas during a same period.
 9. Thetransposition circuit of claim 8, wherein N=4.
 10. The transpositioncircuit of claim 8, wherein the N memory units are random accessmemories.